1. Field of the Invention
This invention relates generally to electronic design automation (EDA) systems used for designing integrated circuits. The invention is more specifically related to a method and apparatus for identifying gated clocks within a circuit design using a standard EDA optimization tool during the integrated circuit design process.
2. Description of the Prior Art
The design process for all integrated circuits is composed of several discrete operations. Initially, the proposed functionality for a circuit is analyzed by one or more chip designers. These designers define the logical components of the circuit and their interactions by specifying the logic design using design capture tools. These design capture tools are commonly implemented in software executing on an engineering workstation, with well-known input devices being used to receive design information from the chip designer, and output devices, such as computer displays, being used to provide visual feedback of the design to the designer as it is being constructed. Such software is typically implemented as part of an electronic design automation (EDA) system. Specifically, the design entry operation involves generating a description of the logic design to be implemented on the circuit chip in an appropriate machine-readable form. Chip designers generally employ hierarchial design techniques to determine the appropriate selection and interconnection of logic and/or memory devices which will enable the chip to perform the desired function. These techniques involve describing the chip's functionality at various levels of abstraction, ranging from the most general function performed by the chip to the precise functions performed by each logic and/or memory element on the chip.
A common method for specifying the integrated circuit design is the use of hardware description languages. This method allows a circuit designer to specify the circuit at the register transfer level (also known as a "behavior description"). Using this method, the circuit is defined in small building blocks. The names of the building blocks are specified by the circuit designer. Thus, they usually are logical names with specific functional meaning.
Encoding the design in a hardware description language (HDL) is a major design entry technique used to specify modern integrated circuits. Hardware description languages are specifically developed to aid a designer in describing a circuit. These languages often contain specific functions and syntax to allow complex hardware structures to be described in a compact and efficient way.
It is useful to distinguish between those components of an integrated circuit design called cells, provided by a silicon chip vendor as primitive cells (i.e., leaf candidates), and the user-defined hierarchy blocks built upon them. One way is to speak of a "cell library" vs. a "design library" as two separate libraries, both of which are available to subsequent designs. Alternatively, at least initially, a design library contains a cell library. A cell library is a database containing detailed specifications on the characteristics of each logical component available for use in a design. Initial cell library contents are usually provided by the chip vendor. The components in the cell library are identified by the generic description of the component type. For example, the term "NAND" for a NAND gate is its type description and distinguishes this component from others such as OR gates, flip-flops, multiplexors, and so on. A two-input NAND gate might be of type 2NAND. When a 2NAND component is specified as part of a given circuit design, it is given an instance name, to distinguish it from all other 2NAND gates used in the circuit. The instance name typically includes the instance names of all parent instances by concatenation when defining the instance in the context of the chip.
A single name is sufficient when dealing only in the context of a single user function. The user-defined blocks can then be used to design larger blocks of greater complexity. The user-defined blocks are added to the design library, which grows from the additions of new design modules as the design evolves. The top level of the design hierarchy may be a single block that defines the entire design, and the bottom layer of the hierarchy may consist of leaf cells, the cells (i.e., the logical components) that were originally provided in the cell library. The resulting design is often called a detailed (or gate-level) description of the logic design.
The generation of the detailed description is often accomplished by logic design synthesis software for HDL entry. The logic design synthesis software generates a gate-level description of user-defined input and output logic, and also creates new gate-level logic to implement user-defined logical functions. Typically, the logic design synthesis software is executed many times during the integrated circuit design process, because errors may be detected during the simulation and testing phases of the design cycle and then fixed in the behavioral description.
The output of the design capture and synthesis tools is typically a logic design database which completely specifies the logical and functional relationships among the components of the design. Once the design has been converted into this form, it may be optimized by sending the logic design database to a logic optimizer tool typically implemented in software.
In many logic optimizer tools, the optimization process may include a characterization step and an optimization step. During the characterization step, various optimization parameters are assigned to selected portions of the design. For example, for those portions of the design that are to be optimized for timing, the characterization step may perform a timing analysis of the design, and identify critical paths within the design that need to be improved by optimization. The characterization step may then assign timing constraints to those portions of the design, indicating the degree that they must be optimized to meet the desired timing goals.
After the characterization step is complete, the optimizer tool may perform an optimization step. The optimization step typically attempts to optimize the design such that all of the timing constraints assigned by the characterization step are satisfied. During the optimization step, the logic optimizer may, for example, remove logic from the design that is unnecessary, minimize the logic that is necessary to implement certain functions, increase the power of selected cells to improve performance, etc.
After the design has been optimized, the circuit designers typically verify that the resulting logic definition is correct and that the integrated circuit implements the expected function. This verification is currently achieved by timing and simulation software tools. The design undergoes design verification analysis in order to detect flaws in the design. The design is also analyzed by simulating the design to assess the functionality of the design. If errors are found or the resulting functionality is unacceptable, the designer modifies the behavior description as needed. These design iterations help to ensure that the design satisfies the desired requirements.
After timing verifications and functional simulation have been completed, placement and routing of the design's components is performed. These steps involve allocating components of the design to locations on the integrated circuit chip and interconnecting the components to form nets. Finally, final timing verification is performed after placement and routing is complete.
A problem in the above design process may occur when gated clocking schemes are used in the design. That is, typical logic optimizer tools can only handle standard clocking schemes, such as where a number of clock signals are independently generated and distributed throughout the system, and each state device in the design is coupled to only one of the clock signals. For high performance designs, however, it is often desirable to use gated clocking schemes to increase the density and performance of the design, and to ease the difficulty of placing and routing the various clock trees. It has been found that a gated clocking scheme can increase the performance of a design by as much as 10-20 percent over standard clock schemes. Further, the use of a gated clocking scheme can reduce the number of raw clock signals that must be routed throughout the design, and thus the number of critical clock nets within the design.
In a gated clock scheme, both a clock enable signal and a raw clock signal may be provided to a logic gate, wherein the output of the logic gate may provide a "gated clock" signal to the corresponding state devices. Typically, the clock enable signals may have a substantially wider pulse width than the raw clock signals, and may easily envelope the corresponding clock pulses. Thus, the logic used to distribute the clock enable signals is generally not subject to the same timing constraints as the clock trees used to distribute the raw clock signals. For this reasons, the logic used to distribute the clock enable signals can typically be automatically placed and routed, without any special consideration given thereto.
In contrast, the clock trees that distribute the raw clock signals must typically either be manually placed and routed within the design, or priority routing channels must be assigned to those nets during the auto place and route process. In either case, the designer typically must compare the corresponding net lengths for each of the raw clock trees to ensure that the clock skew between the resulting raw clock signals is minimized. As can readily be seen, a gated clocking scheme may reduce the number of critical raw clock signals by providing a number of less sensitive clock enable signals, and thus may reduce the overall complexity of placing and routing the clocking network.
Logic Optimizer tools typically use clock information during the logic optimization process to optimize the overall design. Such clock information typically identifies a particular clock signal for each of the state devices within the design. For example, the clock information may identify each state device within the design that is controlled by each clock signal. The logic optimizer tool may then calculate the maximum allowed propagation time between any two registers in the design by identifying the corresponding clock signals that are associated therewith.
The clocking information may be provided to the logic optimizer tool in any number of ways. For example, the user may provide a list of the ASIC pins that are used as clock inputs, and/or the instance names of drivers contained within the design that generate the clock signals. To identify the particular clock signal that corresponds to each state device, the logic optimizer tool may include a tracing capability, wherein the tracing capability may trace each clock signal from the pre-identified clock source to the corresponding state devices, thereby identifying a correspondence between the various clock signals and the number of state devices.
A limitation of the above clock identifying method is that the tracing scheme provided by the logic optimizer tool may not properly identify the correct clock in designs that use gated clocking schemes. That is, when the raw clock signals are traced to the corresponding state devices, the clock enable signals may not be identified or taken into account. Accordingly, the above-referenced clock tracing scheme may incorrectly associate a raw clock signal with each state device, rather than the correct gated clock signal. It is recognized that it may be possible to provide the logic optimizer tools with the proper clock information by manually assembling a clock list with the appropriate clocking information, including the gated clocking information. However, for large designs, this is a prohibitively large task, and extremely tedious.